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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-07 13:32:09 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-07 13:32:09 +0000
commit4cc633c38bb785bc9e586fa26b9a9e22bb41200c (patch)
tree29bde3fe830d376b7a768f95a0c765336e1e0b69 /target-arm/translate.c
parentaaf2d97dcbc4f43f086bcf356a2e31b7dbd6b775 (diff)
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Patch holes in ARM translation (Laurent Desnogues).
- gen_set_CF_bit31: use the right value to set carry flag - shifter_out_im: remove a spurious semi-colon - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN size 2 case - sbfx, ubfx are v6t2 instructions The correct cps user mode behaviour is unclear so it's left out from the commit until ARM decides it. Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5908 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/translate.c')
-rw-r--r--target-arm/translate.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 680a890..94528be 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -415,7 +415,7 @@ static void gen_set_CF_bit31(TCGv var)
{
TCGv tmp = new_tmp();
tcg_gen_shri_i32(tmp, var, 31);
- gen_set_CF(var);
+ gen_set_CF(tmp);
dead_tmp(tmp);
}
@@ -490,7 +490,7 @@ static void shifter_out_im(TCGv var, int shift)
tcg_gen_andi_i32(tmp, var, 1);
} else {
tcg_gen_shri_i32(tmp, var, shift);
- if (shift != 31);
+ if (shift != 31)
tcg_gen_andi_i32(tmp, tmp, 1);
}
gen_set_CF(tmp);
@@ -4618,6 +4618,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
imm = (uint32_t)shift;
tmp2 = tcg_const_i32(imm);
TCGV_UNUSED_I64(tmp64);
+ break;
case 3:
tmp64 = tcg_const_i64(shift);
TCGV_UNUSED(tmp2);
@@ -6583,6 +6584,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
break;
case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
+ ARCH(6T2);
tmp = load_reg(s, rm);
shift = (insn >> 7) & 0x1f;
i = ((insn >> 16) & 0x1f) + 1;