diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:22 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:12:41 +0000 |
| commit | 30b05bba1122c13206d85d3704e86ff30cc09750 (patch) | |
| tree | 07e5152cccb7c762457497e68c7050b9d81bbabe /target-arm/translate.c | |
| parent | b22af022b22091f22deead5f0cbea332b6280acb (diff) | |
| download | qemu-30b05bba1122c13206d85d3704e86ff30cc09750.zip qemu-30b05bba1122c13206d85d3704e86ff30cc09750.tar.gz qemu-30b05bba1122c13206d85d3704e86ff30cc09750.tar.bz2 | |
target-arm: Move block cache ops to new cp15 framework
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/translate.c')
| -rw-r--r-- | target-arm/translate.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index f4e9435..fcdc9d3 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; if ((insn & (1 << 25)) == 0) { - if (insn & (1 << 20)) { - /* mrrc */ - return 1; - } - /* mcrr. Used for block cache operations, so implement as no-op. */ - return 0; + return 1; } if ((insn & (1 << 4)) == 0) { /* cdp */ |