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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-23 15:36:43 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 15:09:41 +0000 |
| commit | 235ea1f5c89abf30e452539b973b0dbe43d3fe2b (patch) | |
| tree | 926cd2da5ac6f850018a29d2a2a5226ed19e1e95 /target-arm/op_helper.c | |
| parent | 4d1e324b2241017c92d816ec3af51a14685dbf62 (diff) | |
| download | qemu-235ea1f5c89abf30e452539b973b0dbe43d3fe2b.zip qemu-235ea1f5c89abf30e452539b973b0dbe43d3fe2b.tar.gz qemu-235ea1f5c89abf30e452539b973b0dbe43d3fe2b.tar.bz2 | |
target-arm: Give CPSR setting on 32-bit exception return its own helper
The rules for setting the CPSR on a 32-bit exception return are
subtly different from those for setting the CPSR via an instruction
like MSR or CPS. (In particular, in Hyp mode changing the mode bits
is not valid via MSR or CPS.) Split the exception-return case into
its own helper for setting CPSR, so we can eventually handle them
differently in the helper function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-2-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/op_helper.c')
| -rw-r--r-- | target-arm/op_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 538887c..e3ddd5a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -425,6 +425,12 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) cpsr_write(env, val, mask); } +/* Write the CPSR for a 32-bit exception return */ +void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) +{ + cpsr_write(env, val, CPSR_ERET_MASK); +} + /* Access to user mode registers from privileged modes. */ uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno) { |