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authorbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2005-02-22 19:27:29 +0000
committerbellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>2005-02-22 19:27:29 +0000
commitb7bcbe9524c05d5134136cce2d5d2a09c09a4f83 (patch)
treeeca1dfcc0112e820adf13e28f1c24c486f11ba09 /target-arm/exec.h
parent55754d9ef27178cf0e13aea85062fc4c32e25f83 (diff)
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ARM VFP support (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/exec.h')
-rw-r--r--target-arm/exec.h32
1 files changed, 28 insertions, 4 deletions
diff --git a/target-arm/exec.h b/target-arm/exec.h
index e17302e..64fce71 100644
--- a/target-arm/exec.h
+++ b/target-arm/exec.h
@@ -24,13 +24,16 @@ register uint32_t T0 asm(AREG1);
register uint32_t T1 asm(AREG2);
register uint32_t T2 asm(AREG3);
+/* TODO: Put these in FP regs on targets that have such things. */
+/* It is ok for FT0s and FT0d to overlap. Likewise FT1s and FT1d. */
+#define FT0s env->vfp.tmp0s
+#define FT1s env->vfp.tmp1s
+#define FT0d env->vfp.tmp0d
+#define FT1d env->vfp.tmp1d
+
#include "cpu.h"
#include "exec-all.h"
-void cpu_lock(void);
-void cpu_unlock(void);
-void cpu_loop_exit(void);
-
/* Implemented CPSR bits. */
#define CACHED_CPSR_BITS 0xf8000000
static inline int compute_cpsr(void)
@@ -51,3 +54,24 @@ static inline void regs_to_env(void)
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu);
+
+/* In op_helper.c */
+
+void cpu_lock(void);
+void cpu_unlock(void);
+void cpu_loop_exit(void);
+
+void raise_exception(int);
+
+void do_vfp_abss(void);
+void do_vfp_absd(void);
+void do_vfp_negs(void);
+void do_vfp_negd(void);
+void do_vfp_sqrts(void);
+void do_vfp_sqrtd(void);
+void do_vfp_cmps(void);
+void do_vfp_cmpd(void);
+void do_vfp_cmpes(void);
+void do_vfp_cmped(void);
+void do_vfp_set_fpscr(void);
+void do_vfp_get_fpscr(void);