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authorPeter Maydell <peter.maydell@linaro.org>2016-02-11 11:17:30 +0000
committerPeter Maydell <peter.maydell@linaro.org>2016-02-11 11:17:30 +0000
commit5513c3abed8e5fabe116830c63f0d3fe1f94bd21 (patch)
tree904144976ca6497e45e6cc11089b285e81652a47 /target-arm/cpu.h
parent6b7f0b61f080b886c9b4bba8240379ce90e20b12 (diff)
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target-arm: Implement MDCR_EL3 and SDCR
Implement the MDCR_EL3 register (which is SDCR for AArch32). For the moment we implement it as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 52284e9..cf2df50 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -382,6 +382,7 @@ typedef struct CPUARMState {
uint64_t mdscr_el1;
uint64_t oslsr_el1; /* OS Lock Status */
uint64_t mdcr_el2;
+ uint64_t mdcr_el3;
/* If the counter is enabled, this stores the last time the counter
* was reset. Otherwise it stores the counter value
*/