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authorPeter Maydell <peter.maydell@linaro.org>2015-09-07 10:39:28 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-09-07 10:39:28 +0100
commit8012c84ff92a36d05dfe61af9b24dd01a7ea25e4 (patch)
tree9aac5bee6b1e79b5c943c8c26a5c90eb3d0c9f42 /target-arm/cpu.h
parent7446d35e1dd69e1da8241277eae09e293741b362 (diff)
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target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction
For the A64 instruction set, the semihosting call instruction is 'HLT 0xf000'. Wire this up to call do_arm_semihosting() if semihosting is enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christopher Covington <christopher.covington@linaro.org> Tested-by: Christopher Covington <cov@codeaurora.org> Message-id: 1439483745-28752-10-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 0a25335..c794afc 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -56,6 +56,7 @@
#define EXCP_SMC 13 /* Secure Monitor Call */
#define EXCP_VIRQ 14
#define EXCP_VFIQ 15
+#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2