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| author | Greg Bellows <greg.bellows@linaro.org> | 2015-05-29 11:28:51 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-05-29 11:28:51 +0100 |
| commit | 012a906b19e99b126403ff4a257617dab9b34163 (patch) | |
| tree | 5f1e0e8c46dcf6ee493ecb2d08d6b4e738a469cd /target-arm/cpu.h | |
| parent | c63285991b371c031147ad620dd7671662a90303 (diff) | |
| download | qemu-012a906b19e99b126403ff4a257617dab9b34163.zip qemu-012a906b19e99b126403ff4a257617dab9b34163.tar.gz qemu-012a906b19e99b126403ff4a257617dab9b34163.tar.bz2 | |
target-arm: Update interrupt handling to use target EL
Updated the interrupt handling to utilize and report through the target EL
exception field. This includes consolidating and cleaning up code where
needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and
do_interrupt was updated to use the target_el exception field. The
necessary code from arm_excp_target_el() was merged in where needed and the
function removed.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1429722561-12651-4-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6845666..9119a94 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1000,7 +1000,8 @@ static inline bool access_secure_reg(CPUARMState *env) (_val)) void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf); -unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx); +uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, + uint32_t cur_el, bool secure); /* Interface between CPU and Interrupt controller. */ void armv7m_nvic_set_pending(void *opaque, int irq); @@ -1482,11 +1483,11 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, + unsigned int target_el) { CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_el(env); - unsigned int target_el = arm_excp_target_el(cs, excp_idx); bool secure = arm_is_secure(env); uint32_t scr; uint32_t hcr; |