diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:05 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:05 +0000 |
commit | a7adc4b779d24e75d05d43fb6311ab9e6449523a (patch) | |
tree | dd519d603db6d8f52a4b4ca397afc92a0b90a56c /target-arm/cpu.h | |
parent | 4b7fff2fabeaa3d13e23b249b855f39f0921048d (diff) | |
download | qemu-a7adc4b779d24e75d05d43fb6311ab9e6449523a.zip qemu-a7adc4b779d24e75d05d43fb6311ab9e6449523a.tar.gz qemu-a7adc4b779d24e75d05d43fb6311ab9e6449523a.tar.bz2 |
target-arm: Implement AArch64 generic timers
Implement the AArch64 view of the generic timer system registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r-- | target-arm/cpu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4bbc9ad..4edb659 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -104,7 +104,7 @@ struct arm_boot_info; /* CPU state for each instance of a generic timer (in cp15 c14) */ typedef struct ARMGenericTimer { uint64_t cval; /* Timer CompareValue register */ - uint32_t ctl; /* Timer Control register */ + uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; #define GTIMER_PHYS 0 @@ -204,8 +204,8 @@ typedef struct CPUARMState { uint64_t tpidr_el0; /* User RW Thread register. */ uint64_t tpidrro_el0; /* User RO Thread register. */ uint64_t tpidr_el1; /* Privileged Thread register. */ - uint32_t c14_cntfrq; /* Counter Frequency register */ - uint32_t c14_cntkctl; /* Timer Control register */ + uint64_t c14_cntfrq; /* Counter Frequency register */ + uint64_t c14_cntkctl; /* Timer Control register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; uint32_t c15_cpar; /* XScale Coprocessor Access Register */ uint32_t c15_ticonfig; /* TI925T configuration byte. */ |