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| author | Fabian Aggeler <aggelerf@ethz.ch> | 2014-12-11 12:07:50 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-12-11 12:07:50 +0000 |
| commit | e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 (patch) | |
| tree | e9425f4debfa74fdd29051e418f45f46472d6ff1 /target-arm/cpu.h | |
| parent | 144634ae6c1618dcee6aced9c0d4427844154091 (diff) | |
| download | qemu-e89e51a17ea0d8aef9bf9b766c98f963e835fbf2.zip qemu-e89e51a17ea0d8aef9bf9b766c98f963e835fbf2.tar.gz qemu-e89e51a17ea0d8aef9bf9b766c98f963e835fbf2.tar.bz2 | |
target-arm: add MVBAR support
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-13-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 12bd6ec..cdf2dd7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -211,6 +211,7 @@ typedef struct CPUARMState { uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; uint64_t vbar_el[4]; /* vector base address register */ + uint32_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ |