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| author | Davorin Mista <davorin.mista@aggios.com> | 2015-10-16 11:14:53 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-16 11:14:53 +0100 |
| commit | 1424ca8d4320427c3e93722b65e19077969808a2 (patch) | |
| tree | b91a21fdec9893333f64574a9b134d5dba22e5ff /target-arm/cpu.h | |
| parent | bab27ea2e3855b6495a743f19b9d28cb013443ea (diff) | |
| download | qemu-1424ca8d4320427c3e93722b65e19077969808a2.zip qemu-1424ca8d4320427c3e93722b65e19077969808a2.tar.gz qemu-1424ca8d4320427c3e93722b65e19077969808a2.tar.bz2 | |
target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs
Added oslar_write function to OSLAR_EL1 sysreg, using a status variable
in ARMCPUState.cp15 struct (oslsr_el1). This variable is also linked
to the newly added read-only OSLSR_EL1 register.
Linux reads from this register during its suspend/resume procedure.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
[PMM: folded a long line and tweaked a comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5fb0479..d1b5bc1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -379,6 +379,7 @@ typedef struct CPUARMState { uint64_t dbgwvr[16]; /* watchpoint value registers */ uint64_t dbgwcr[16]; /* watchpoint control registers */ uint64_t mdscr_el1; + uint64_t oslsr_el1; /* OS Lock Status */ /* If the counter is enabled, this stores the last time the counter * was reset. Otherwise it stores the counter value */ |