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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-18 00:02:17 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-09-18 00:02:17 +0000 |
| commit | 6ad025921c4d6e63e7065ba084ffe6ddf709c4de (patch) | |
| tree | 07653d52b627662aac5f68a045b4d9004cef8871 /target-alpha/translate.c | |
| parent | b3249f630e95f3235da438ee1a6cd1b867084e9c (diff) | |
| download | qemu-6ad025921c4d6e63e7065ba084ffe6ddf709c4de.zip qemu-6ad025921c4d6e63e7065ba084ffe6ddf709c4de.tar.gz qemu-6ad025921c4d6e63e7065ba084ffe6ddf709c4de.tar.bz2 | |
target-alpha: switch a few helpers to TCG
Switch a few helpers to TCG and implement RC and RS instructions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-alpha/translate.c')
| -rw-r--r-- | target-alpha/translate.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 583fa86..1b93767 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -250,8 +250,14 @@ static always_inline void _gen_op_bcond (DisasContext *ctx) static always_inline void gen_excp (DisasContext *ctx, int exception, int error_code) { + TCGv tmp1, tmp2; + tcg_gen_movi_i64(cpu_pc, ctx->pc); - gen_op_excp(exception, error_code); + tmp1 = tcg_const_i32(exception); + tmp2 = tcg_const_i32(error_code); + tcg_gen_helper_0_2(helper_excp, tmp1, tmp2); + tcg_temp_free(tmp2); + tcg_temp_free(tmp1); } static always_inline void gen_invalid (DisasContext *ctx) @@ -1176,9 +1182,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x6C: /* IMPLVER */ - gen_op_load_implver(); if (rc != 31) - tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]); + tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]); break; default: goto invalid_opc; @@ -1699,16 +1704,13 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0xC000: /* RPCC */ - gen_op_load_pcc(); if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); + tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]); break; case 0xE000: /* RC */ - gen_op_load_irf(); if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); - gen_op_clear_irf(); + tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]); break; case 0xE800: /* ECB */ @@ -1721,10 +1723,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0xF000: /* RS */ - gen_op_load_irf(); if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); - gen_op_set_irf(); + tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]); break; case 0xF800: /* WH64 */ |