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authorRichard Henderson <richard.henderson@linaro.org>2022-04-29 13:59:52 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-06-28 04:35:07 +0530
commit3c820ddc1b92f17fea85fdaed2928feaa9c238d7 (patch)
tree3c1bccb9e500c73c7a0923fe2ab235a858c3dfb0 /semihosting
parentef9c5ea85d83459361449259418726a5d4d0a751 (diff)
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semihosting: Split common_semi_flen_buf per target
We already have some larger ifdef blocks for ARM and RISCV; split out common_semi_stack_bottom per target. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'semihosting')
-rw-r--r--semihosting/arm-compat-semi.c44
1 files changed, 21 insertions, 23 deletions
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index d2ce214..7550dce 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -217,6 +217,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
{
return is_a64(env);
}
+
+static inline target_ulong common_semi_stack_bottom(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ return is_a64(env) ? env->xregs[31] : env->regs[13];
+}
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
@@ -246,6 +253,13 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
{
return riscv_cpu_mxl(env) != MXL_RV32;
}
+
+static inline target_ulong common_semi_stack_bottom(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ return env->gpr[xSP];
+}
#endif
/*
@@ -301,31 +315,15 @@ static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
common_semi_set_ret(cs, ret);
}
+/*
+ * Return an address in target memory of 64 bytes where the remote
+ * gdb should write its stat struct. (The format of this structure
+ * is defined by GDB's remote protocol and is not target-specific.)
+ * We put this on the guest's stack just below SP.
+ */
static target_ulong common_semi_flen_buf(CPUState *cs)
{
- target_ulong sp;
-#ifdef TARGET_ARM
- /* Return an address in target memory of 64 bytes where the remote
- * gdb should write its stat struct. (The format of this structure
- * is defined by GDB's remote protocol and is not target-specific.)
- * We put this on the guest's stack just below SP.
- */
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
- if (is_a64(env)) {
- sp = env->xregs[31];
- } else {
- sp = env->regs[13];
- }
-#endif
-#ifdef TARGET_RISCV
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
-
- sp = env->gpr[xSP];
-#endif
-
+ target_ulong sp = common_semi_stack_bottom(cs);
return sp - 64;
}