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| author | eopXD <yueh.ting.chen@gmail.com> | 2022-06-06 06:16:16 +0000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-06-10 09:31:42 +1000 |
| commit | 752614cab8e61bb6ba96cee1ec127eba6c35398e (patch) | |
| tree | 486e8ed3a02e0272a7da9be35d07d5b48761e985 /scsi | |
| parent | f1eed927fb3a1212af8e324cf242cf6f4bd6fd04 (diff) | |
| download | qemu-752614cab8e61bb6ba96cee1ec127eba6c35398e.zip qemu-752614cab8e61bb6ba96cee1ec127eba6c35398e.tar.gz qemu-752614cab8e61bb6ba96cee1ec127eba6c35398e.tar.bz2 | |
target/riscv: rvv: Add tail agnostic for vector load / store instructions
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail elements.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <165449614532.19704.7000832880482980398-6@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scsi')
0 files changed, 0 insertions, 0 deletions