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| author | Zhao Liu <zhao1.liu@intel.com> | 2025-07-11 18:21:43 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-07-12 15:28:22 +0200 |
| commit | 2141898bb9b7f3d426871eaa6e98b4c77a1f81e8 (patch) | |
| tree | cd2f61ab9346a634d1e78ecaeb9d8a16906d58ab /scripts | |
| parent | 25acae4c6e7635ff0f0d36945548de4c0dc70608 (diff) | |
| download | qemu-2141898bb9b7f3d426871eaa6e98b4c77a1f81e8.zip qemu-2141898bb9b7f3d426871eaa6e98b4c77a1f81e8.tar.gz qemu-2141898bb9b7f3d426871eaa6e98b4c77a1f81e8.tar.bz2 | |
i386/cpu: Use a unified cache_info in X86CPUState
At present, all cases using the cache model (CPUID 0x2, 0x4, 0x80000005,
0x80000006 and 0x8000001D leaves) have been verified to be able to
select either cache_info_intel or cache_info_amd based on the vendor.
Therefore, further merge cache_info_intel and cache_info_amd into a
unified cache_info in X86CPUState, and during its initialization, set
different legacy cache models based on the vendor.
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Link: https://lore.kernel.org/r/20250711102143.1622339-19-zhao1.liu@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions