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| author | Jim Shu <jim.shu@sifive.com> | 2025-05-19 22:35:18 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:48 +1000 |
| commit | dff5f515409f1c9c10df00160524b21381cbef26 (patch) | |
| tree | 7a40811901b8551bdf62d7ebdd9812b48a458d90 /scripts/tracetool/backend/log.py | |
| parent | 3cb2edae740121cf5da3a9adb8190051e866eb01 (diff) | |
| download | qemu-dff5f515409f1c9c10df00160524b21381cbef26.zip qemu-dff5f515409f1c9c10df00160524b21381cbef26.tar.gz qemu-dff5f515409f1c9c10df00160524b21381cbef26.tar.bz2 | |
target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed
Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we
also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250519143518.11086-5-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/tracetool/backend/log.py')
0 files changed, 0 insertions, 0 deletions