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| author | Huang Borong <3543977024@qq.com> | 2025-04-25 20:22:12 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-07-04 21:09:49 +1000 |
| commit | 60aab7ad11e6cd8a82420ed6a18416853c0fb762 (patch) | |
| tree | 02c0a3fe00f02747640b56b077e4f465d823045b /scripts/tracetool/backend/log.py | |
| parent | 2454fc95ece3c73f649e21621775bcbe859d28ec (diff) | |
| download | qemu-60aab7ad11e6cd8a82420ed6a18416853c0fb762.zip qemu-60aab7ad11e6cd8a82420ed6a18416853c0fb762.tar.gz qemu-60aab7ad11e6cd8a82420ed6a18416853c0fb762.tar.bz2 | |
target/riscv: Add BOSC's Xiangshan Kunminghu CPU
Add a CPU entry for the Xiangshan Kunminghu CPU, an open-source,
high-performance RISC-V processor. More details can be found at:
https://github.com/OpenXiangShan/XiangShan
Note: The ISA extensions supported by the Xiangshan Kunminghu CPU are
categorized based on four RISC-V specifications: Volume I: Unprivileged
Architecture, Volume II: Privileged Architecture, AIA, and RVA23. The
extensions within each category are organized according to the chapter
order in the specifications.
Signed-off-by: Yu Hu <huyu@bosc.ac.cn>
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
Signed-off-by: Borong Huang <3543977024@qq.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250425122212.364-1-wangran@bosc.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/tracetool/backend/log.py')
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