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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:49 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:06 +0100 |
| commit | f318cec6adcb73c688d68b0874686a30c0f34a2e (patch) | |
| tree | fa722ad17c8c35c4fae6391bbd88f007c25e2b9b /scripts/switch-timer-api | |
| parent | 377a44ec8f2fac5b7bef41d212dfbabf53c8c810 (diff) | |
| download | qemu-f318cec6adcb73c688d68b0874686a30c0f34a2e.zip qemu-f318cec6adcb73c688d68b0874686a30c0f34a2e.tar.gz qemu-f318cec6adcb73c688d68b0874686a30c0f34a2e.tar.bz2 | |
target-arm: Implement CBAR for Cortex-A57
The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view; expand the QOM reset-cbar property from UINT32
to UINT64 so this can be specified, and implement the
32-bit and 64-bit views of a 64-bit CBAR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions