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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:46 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:05 +0100 |
| commit | 1090b9c6ccfe837f1c76dafb7e56031bd7844075 (patch) | |
| tree | dcefb350ea9e9d53f395d506c55dd8b2ed14d717 /scripts/qapi-visit.py | |
| parent | 2eef0bf82146034f756d39cb02c8c8dd561a8942 (diff) | |
| download | qemu-1090b9c6ccfe837f1c76dafb7e56031bd7844075.zip qemu-1090b9c6ccfe837f1c76dafb7e56031bd7844075.tar.gz qemu-1090b9c6ccfe837f1c76dafb7e56031bd7844075.tar.bz2 | |
target-arm: Implement ISR_EL1 register
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'scripts/qapi-visit.py')
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