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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-18 09:31:22 -0500 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-10-04 10:25:23 +1000 |
| commit | bc7a45ab88281bbced8ebe9fb87d518102b22519 (patch) | |
| tree | 15b3077a2beb005d490bfe320de33cfb499cccf4 /qtest.c | |
| parent | a2735cf483814b1c0e5773eee4a52f8e32d438cf (diff) | |
| download | qemu-bc7a45ab88281bbced8ebe9fb87d518102b22519.zip qemu-bc7a45ab88281bbced8ebe9fb87d518102b22519.tar.gz qemu-bc7a45ab88281bbced8ebe9fb87d518102b22519.tar.bz2 | |
ppc: Add support for 'mffsce' instruction
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
This patch adds support for 'mffsce' instruction.
'mffsce' is identical to 'mffs', except that it also clears the exception
enable bits in the FPSCR.
On CPUs without support for 'mffsce' (below ISA 3.0), the
instruction will execute identically to 'mffs'.
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'qtest.c')
0 files changed, 0 insertions, 0 deletions