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| author | Cédric Le Goater <clg@kaod.org> | 2022-08-17 17:08:20 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-08-31 14:08:06 -0300 |
| commit | 4a7d2b7e5cebd00bdcc842517174ad33fd4934cb (patch) | |
| tree | fe953067f4153747da8a2858f9bf2d2ecce1f666 /qobject | |
| parent | 629cae617039e03d5bfdc0120ade69135a009d33 (diff) | |
| download | qemu-4a7d2b7e5cebd00bdcc842517174ad33fd4934cb.zip qemu-4a7d2b7e5cebd00bdcc842517174ad33fd4934cb.tar.gz qemu-4a7d2b7e5cebd00bdcc842517174ad33fd4934cb.tar.bz2 | |
ppc/ppc405: QOM'ify CPC
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'qobject')
0 files changed, 0 insertions, 0 deletions