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| author | lixinyu <precinct@mail.ustc.edu.cn> | 2020-04-11 20:46:12 +0800 |
|---|---|---|
| committer | Michael Roth <mdroth@linux.vnet.ibm.com> | 2020-06-22 12:53:09 -0500 |
| commit | 27f56b9aa2687a346484aa2108bbb2f70bc2d373 (patch) | |
| tree | b7a60e2451df874bdfebb5ac043a8f843138fcc2 /qint.c | |
| parent | 97701bc03e0e369efb96c06390df4db6caf675bc (diff) | |
| download | qemu-27f56b9aa2687a346484aa2108bbb2f70bc2d373.zip qemu-27f56b9aa2687a346484aa2108bbb2f70bc2d373.tar.gz qemu-27f56b9aa2687a346484aa2108bbb2f70bc2d373.tar.bz2 | |
tcg/mips: mips sync* encode error
OPC_SYNC_WMB, OPC_SYNC_MB, OPC_SYNC_ACQUIRE, OPC_SYNC_RELEASE and
OPC_SYNC_RMB have wrong encode. According to the mips manual,
their encode should be 'OPC_SYNC | 0x?? << 6' rather than
'OPC_SYNC | 0x?? << 5'. Wrong encode can lead illegal instruction
errors. These instructions often appear with multi-threaded
simulation.
Fixes: 6f0b99104a3 ("tcg/mips: Add support for fence")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: lixinyu <precinct@mail.ustc.edu.cn>
Message-Id: <20200411124612.12560-1-precinct@mail.ustc.edu.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
(cherry picked from commit a4e57084c16d5b0eff3651693fba04f26b30b551)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Diffstat (limited to 'qint.c')
0 files changed, 0 insertions, 0 deletions