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authorIsaku Yamahata <yamahata@valinux.co.jp>2011-04-01 20:43:23 +0900
committerMichael S. Tsirkin <mst@redhat.com>2011-04-01 15:54:03 +0300
commitab431c283e7055bcd6fb622f212bb29e84a6a134 (patch)
tree1978bd7c37bb9980190c9988c3c336f45c355f06 /qemu-tech.texi
parente735b55a8c11dd455e31ccd4420e6c9485191d0c (diff)
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piix_pci: optimize set irq path
optimize irq routing in piix_pic.c which has been a TODO. So far piix3 tracks each pirq level and checks whether a given pic pins is asserted by seeing if each pirq is mapped into the pic pin. This is independent on irq routing, but data path is on slow path. Given that irq routing is rarely changed and asserting pic pins is on data path, the path that asserts pic pins should be optimized and chainging irq routing should be on slow path. The new behavior with this patch series is to use bitmap which is addressed by pirq and pic pins with a given irq routing. When pirq is asserted, the bitmap is set and see if the pic pins is asserted by checking the bitmaps. When irq routing is changed, rebuild the bitmap and re-assert pic pins. test: - create VM with 4 e1000 nics in different pci slots (i.e. fn=0 for each e1000) Thus those e1000's INTA are connected to each PIRQ[A-D]. - run linux as guest and saw each devices triggers interrupt by seeing /proc/interrupts. And then confirmed that each PIRQ[A-D] surely asserted interrupts. Because irq 10 and 11 are shared by 4 e1000's, it only one NIC is activated with ifconfig ethN up/down when counting interrupts. Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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