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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:29:37 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-02-15 18:29:49 +0000 |
| commit | 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b (patch) | |
| tree | 46dc892a0c6393c7fb38691d96c3b3ebd06fd08a /qemu-seccomp.c | |
| parent | 43bbce7fbef22adf687dd84934fd0b2f8df807a8 (diff) | |
| download | qemu-24ac0fb129f9ce9dd96901b2377fc6271dc55b2b.zip qemu-24ac0fb129f9ce9dd96901b2377fc6271dc55b2b.tar.gz qemu-24ac0fb129f9ce9dd96901b2377fc6271dc55b2b.tar.bz2 | |
hw/intc/armv7m_nvic: Implement SCR
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180209165810.6668-7-peter.maydell@linaro.org
Diffstat (limited to 'qemu-seccomp.c')
0 files changed, 0 insertions, 0 deletions