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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-07-12 12:34:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-07-12 12:34:41 +0100 |
| commit | 74e1b782b34e280b06a90f61fdbac5a046cbe491 (patch) | |
| tree | 4e707525686a8c338ec5b013189a5f0d586e89a3 /qemu-doc.texi | |
| parent | c1ac514a0444cae0a822dd9a0e60ac77918c102c (diff) | |
| parent | cdc46fab07a122dfcc8a1054510a68d936ae3440 (diff) | |
| download | qemu-74e1b782b34e280b06a90f61fdbac5a046cbe491.zip qemu-74e1b782b34e280b06a90f61fdbac5a046cbe491.tar.gz qemu-74e1b782b34e280b06a90f61fdbac5a046cbe491.tar.bz2 | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging
MIPS patches 2016-07-12
Changes:
* support 10-bit ASIDs
* MIPS64R6-generic renamed to I6400
* initial GIC support
* implement RESET_BASE register in CM GCR
# gpg: Signature made Tue 12 Jul 2016 11:49:50 BST
# gpg: using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B
* remotes/lalrae/tags/mips-20160712:
target-mips: enable 10-bit ASIDs in I6400 CPU
target-mips: support CP0.Config4.AE bit
target-mips: change ASID type to hold more than 8 bits
target-mips: add ASID mask field and replace magic values
target-mips: replace MIPS64R6-generic with the real I6400 CPU model
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/mips_cpc: make VP correctly start from the reset vector
target-mips: add exception base to MIPS CPU
hw/mips/cps: create GIC block inside CPS
hw/mips: implement Global Interrupt Controller
hw/mips: implement GIC Interval Timer
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qemu-doc.texi')
0 files changed, 0 insertions, 0 deletions