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| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2021-07-19 19:21:09 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-09-30 14:50:20 +0200 |
| commit | 5c76b651d0f6c420d31e51d22c380a0bdd04fb98 (patch) | |
| tree | 21d984064b70b8635f4851893317f13901a96f5b /qapi | |
| parent | dfce81f1b931352af0fcfe966c115a09646bd15a (diff) | |
| download | qemu-5c76b651d0f6c420d31e51d22c380a0bdd04fb98.zip qemu-5c76b651d0f6c420d31e51d22c380a0bdd04fb98.tar.gz qemu-5c76b651d0f6c420d31e51d22c380a0bdd04fb98.tar.bz2 | |
i386: Add primary SGX CPUID and MSR defines
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled (in FEATURE_CONTROL).
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'qapi')
0 files changed, 0 insertions, 0 deletions