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author | Peter Maydell <peter.maydell@linaro.org> | 2019-05-07 12:55:04 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2019-05-07 12:55:04 +0100 |
commit | f1e2598c46d480c9e21213a244bc514200762828 (patch) | |
tree | 367353f17159f60700969b5153b9f31beb20e538 /qapi/string-output-visitor.c | |
parent | a03ffaefce5dbb455ee1bc7c7709faf377dfbd45 (diff) | |
download | qemu-f1e2598c46d480c9e21213a244bc514200762828.zip qemu-f1e2598c46d480c9e21213a244bc514200762828.tar.gz qemu-f1e2598c46d480c9e21213a244bc514200762828.tar.bz2 |
target/arm: Implement XPSR GE bits
In the M-profile architecture, if the CPU implements the DSP extension
then the XPSR has GE bits, in the same way as the A-profile CPSR. When
we added DSP extension support we forgot to add support for reading
and writing the GE bits, which are stored in env->GE. We did put in
the code to add XPSR_GE to the mask of bits to update in the v7m_msr
helper, but forgot it in v7m_mrs. We also must not allow the XPSR we
pull off the stack on exception return to set the nonexistent GE bits.
Correct these errors:
* read and write env->GE in xpsr_read() and xpsr_write()
* only set GE bits on exception return if DSP present
* read GE bits for MRS if DSP present
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190430131439.25251-5-peter.maydell@linaro.org
Diffstat (limited to 'qapi/string-output-visitor.c')
0 files changed, 0 insertions, 0 deletions