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author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2023-08-18 12:40:58 +0900 |
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committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-21 19:35:19 +0300 |
commit | cae7dc14521f6646bf7f9a6a505b2baf354b3320 (patch) | |
tree | 59c862a9ebe15ffeb72b8ddbd9d58b4ec6a709e6 /python/scripts/mkvenv.py | |
parent | 7385e00665b66ab9d7180421b1a69c4e4899c6de (diff) | |
download | qemu-cae7dc14521f6646bf7f9a6a505b2baf354b3320.zip qemu-cae7dc14521f6646bf7f9a6a505b2baf354b3320.tar.gz qemu-cae7dc14521f6646bf7f9a6a505b2baf354b3320.tar.bz2 |
target/riscv: Allocate itrigger timers only once
riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.
Divide riscv_trigger_init() into two functions, namely
riscv_trigger_realize() and riscv_trigger_reset() and call them in
appropriate timing. The timer allocation will happen only once for a
CPU in riscv_trigger_realize().
Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabled")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
(cherry picked from commit a7c272df82af11c568ea83921b04334791dccd5e)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'python/scripts/mkvenv.py')
0 files changed, 0 insertions, 0 deletions