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| author | Damien Hedde <damien.hedde@greensocs.com> | 2020-04-06 15:52:50 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-04-30 15:35:41 +0100 |
| commit | 5b49a34c6800d0cb917f959d8e75e5775f0fac3f (patch) | |
| tree | 962ed8af2d77f48e347ce85e7859c6320490656e /python/qemu/qtest.py | |
| parent | b636db306e06ee1c267d6e15e3b5bc109252617f (diff) | |
| download | qemu-5b49a34c6800d0cb917f959d8e75e5775f0fac3f.zip qemu-5b49a34c6800d0cb917f959d8e75e5775f0fac3f.tar.gz qemu-5b49a34c6800d0cb917f959d8e75e5775f0fac3f.tar.bz2 | |
hw/arm/xilinx_zynq: connect uart clocks to slcr
Add the connection between the slcr's output clocks and the uarts inputs.
Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz
(the default frequency). This clock is used to feed the slcr's input
clock.
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/qtest.py')
0 files changed, 0 insertions, 0 deletions