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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-03-05 16:09:18 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-05 16:09:18 +0000 |
| commit | 38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a (patch) | |
| tree | 9ae03ff18a901b5d1897d4d2beefad2d4e430c9a /python/qemu/accel.py | |
| parent | 1bed4d2e55459129c19f5952bcfc65bd0c70db5b (diff) | |
| download | qemu-38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a.zip qemu-38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a.tar.gz qemu-38262d8a732f8bd0e9ca3dc064f6e73d00c08b9a.tar.bz2 | |
target/arm: Honor the HCR_EL2.TPU bit
This bit traps EL1 access to cache maintenance insns that operate
to the point of unification. There are no longer any references to
plain aa64_cacheop_access, so remove it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/accel.py')
0 files changed, 0 insertions, 0 deletions