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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-03-05 16:09:18 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-05 16:09:18 +0000 |
| commit | 1803d2713b29d85031cc964d545036bda9880f26 (patch) | |
| tree | 0625c10eef2377cf19c2432a0dcc1a2074cf9a7e /python/qemu/accel.py | |
| parent | 84929218512c19ec9a296fbfd7b39219e0c592ae (diff) | |
| download | qemu-1803d2713b29d85031cc964d545036bda9880f26.zip qemu-1803d2713b29d85031cc964d545036bda9880f26.tar.gz qemu-1803d2713b29d85031cc964d545036bda9880f26.tar.bz2 | |
target/arm: Honor the HCR_EL2.TSW bit
These bits trap EL1 access to set/way cache maintenance insns.
Buglink: https://bugs.launchpad.net/bugs/1863685
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/accel.py')
0 files changed, 0 insertions, 0 deletions