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| author | Rémi Denis-Courmont <remi.denis.courmont@huawei.com> | 2021-01-12 12:45:03 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-01-19 14:38:52 +0000 |
| commit | 3d4bd397433b12b148d150c8bc5655a696389bd1 (patch) | |
| tree | 2bad854ecd4e29b0a06951c5cf4516834e5a3a82 /python/qemu/accel.py | |
| parent | c4f060e89effd70ebdb23d3315495d33af377a09 (diff) | |
| download | qemu-3d4bd397433b12b148d150c8bc5655a696389bd1.zip qemu-3d4bd397433b12b148d150c8bc5655a696389bd1.tar.gz qemu-3d4bd397433b12b148d150c8bc5655a696389bd1.tar.bz2 | |
target/arm: do S1_ptw_translate() before address space lookup
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
bits can invert the secure flag for pagetable walks. This patchset
allows S1_ptw_translate() to change the non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-11-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'python/qemu/accel.py')
0 files changed, 0 insertions, 0 deletions