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| author | Babu Moger <babu.moger@amd.com> | 2023-05-04 15:53:09 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2023-05-08 16:35:30 +0200 |
| commit | b70eec312b185197d639bff689007727e596afd1 (patch) | |
| tree | cb6d36af0b4ab6e4a27a13faf61dcc9abd8620e4 /os-win32.c | |
| parent | bb039a230e6a7920d71d21fa9afee2653a678c48 (diff) | |
| download | qemu-b70eec312b185197d639bff689007727e596afd1.zip qemu-b70eec312b185197d639bff689007727e596afd1.tar.gz qemu-b70eec312b185197d639bff689007727e596afd1.tar.bz2 | |
target/i386: Add feature bits for CPUID_Fn80000021_EAX
Add the following feature bits.
no-nested-data-bp : Processor ignores nested data breakpoints.
lfence-always-serializing : LFENCE instruction is always serializing.
null-sel-cls-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Message-Id: <20230504205313.225073-5-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'os-win32.c')
0 files changed, 0 insertions, 0 deletions