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| author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2018-06-01 11:38:08 -0400 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-06-22 15:01:15 -0300 |
| commit | a764f3f7197f4d7ad8fe8424269933de912224cb (patch) | |
| tree | 1938fed38cbd4b47b2bb69c2b7f211c0641f5dc5 /os-win32.c | |
| parent | 9ccb9784b57804f5c74434ad6ccb66650a015ffc (diff) | |
| download | qemu-a764f3f7197f4d7ad8fe8424269933de912224cb.zip qemu-a764f3f7197f4d7ad8fe8424269933de912224cb.tar.gz qemu-a764f3f7197f4d7ad8fe8424269933de912224cb.tar.bz2 | |
i386: define the AMD 'amd-ssbd' CPUID feature bit
AMD future CPUs expose _two_ ways to utilize the Intel equivalant
of the Speculative Store Bypass Disable. The first is via
the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
is via the SPEC_CTRL MSR (0x48). The document titled:
124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=199889
Anyhow, this means that on future AMD CPUs there will be _two_ ways to
deal with SSBD.
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Message-Id: <20180601153809.15259-2-konrad.wilk@oracle.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'os-win32.c')
0 files changed, 0 insertions, 0 deletions