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| author | Yang Weijiang <weijiang.yang@intel.com> | 2022-02-15 14:52:54 -0500 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-05-14 12:32:41 +0200 |
| commit | 301e90675c3fed6cdc48682021a1ab42bc0e0d76 (patch) | |
| tree | 6297ef89365a2456042a1d3feeb9092fc711ccf1 /net | |
| parent | 5a778a5f820fdd907b95e93560637a61f6ea3c71 (diff) | |
| download | qemu-301e90675c3fed6cdc48682021a1ab42bc0e0d76.zip qemu-301e90675c3fed6cdc48682021a1ab42bc0e0d76.tar.gz qemu-301e90675c3fed6cdc48682021a1ab42bc0e0d76.tar.bz2 | |
target/i386: Enable support for XSAVES based features
There're some new features, including Arch LBR, depending
on XSAVES/XRSTORS support, the new instructions will
save/restore data based on feature bits enabled in XCR0 | XSS.
This patch adds the basic support for related CPUID enumeration
and meanwhile changes the name from FEAT_XSAVE_COMP_{LO|HI} to
FEAT_XSAVE_XCR0_{LO|HI} to differentiate clearly the feature
bits in XCR0 and those in XSS.
Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
Message-Id: <20220215195258.29149-5-weijiang.yang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions