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authorLuc Michel <luc@lmichel.fr>2020-10-10 15:57:53 +0200
committerPeter Maydell <peter.maydell@linaro.org>2020-10-27 11:10:44 +0000
commit957458111280e7772cffc1ccbac75a5270e9267f (patch)
tree41c28cc8df093855ecd6389e2fb2de2a0be952fc /net/socket.c
parent09d56bbc9bc2f40865764b06b9830a9504bd3f9a (diff)
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hw/misc/bcm2835_cprman: implement PLL channels behaviour
A PLL channel is able to further divide the generated PLL frequency. The divider is given in the CTRL_A2W register. Some channels have an additional fixed divider which is always applied to the signal. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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