diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-21 08:17:07 -0700 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 08:16:41 -0700 |
commit | be77e1d5fe1abaaf70d886719a4084ea9c0c5eec (patch) | |
tree | 2cad21549339ad49350f7d4bfe8cdad30e45e66d /nbd | |
parent | 34cccb7462e12737f04d59dffeea1389aa689d81 (diff) | |
download | qemu-be77e1d5fe1abaaf70d886719a4084ea9c0c5eec.zip qemu-be77e1d5fe1abaaf70d886719a4084ea9c0c5eec.tar.gz qemu-be77e1d5fe1abaaf70d886719a4084ea9c0c5eec.tar.bz2 |
target/nios2: Clean up handling of tlbmisc in do_exception
The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any
exception with EH=0, or so says Table 42 (Processor Status After
Taking Exception).
We currently do not set PERM or BAD at all, and only set/clear
DBL for tlb miss, and do not clear DBL for any other exception.
It is a bit confusing to set D in tlb_fill and the rest during
do_interrupt, so move the setting of D to do_interrupt as well.
To do this, split EXP_TLBD into two cases, EXCP_TLB_X and EXCP_TLB_D,
which allows us to distinguish them during do_interrupt. Choose
a value for EXCP_TLB_D such that when truncated it produces the
correct value for exception.CAUSE.
Rename EXCP_TLB[RWX] to EXCP_PERM_[RWX], to emphasize that the
exception is permissions related. Rename EXCP_SUPER[AD] to
EXCP_SUPERA_[DX] to emphasize that they are both "supervisor
address" exceptions, data and execute.
Retain the setting of tlbmisc.WE for the fast-tlb-miss path, as it
is being relied upon, but remove it from the permission path.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-37-richard.henderson@linaro.org>
Diffstat (limited to 'nbd')
0 files changed, 0 insertions, 0 deletions