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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-03-03 17:53:41 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-03-03 17:53:41 +0000 |
| commit | b3e54c689c0630e9a79f33a8b03c71296334fd36 (patch) | |
| tree | 6ed0e91140e5213a91430b155f6d193487ea6210 /monitor.c | |
| parent | 88e6c60671df4c8b1b6c1eb8f76950ab1bea0ec2 (diff) | |
| parent | e7dfa64def10e76a33e48a425d18055939c5a60e (diff) | |
| download | qemu-b3e54c689c0630e9a79f33a8b03c71296334fd36.zip qemu-b3e54c689c0630e9a79f33a8b03c71296334fd36.tar.gz qemu-b3e54c689c0630e9a79f33a8b03c71296334fd36.tar.bz2 | |
Merge branch 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa
* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa:
target-xtensa: add breakpoint tests
target-xtensa: add DEBUG_SECTION to overlay tool
target-xtensa: add DBREAK data breakpoints
exec: let cpu_watchpoint_insert accept larger watchpoints
exec: fix check_watchpoint exiting cpu_loop
exec: add missing breaks to the watch_mem_write
target-xtensa: add ICOUNT SR and debug exception
target-xtensa: implement instruction breakpoints
target-xtensa: add DEBUGCAUSE SR and configuration
target-xtensa: fetch 3rd opcode byte only when needed
target-xtensa: implement info tlb monitor command
target-xtensa: define TLB_TEMPLATE for MMU-less cores
Diffstat (limited to 'monitor.c')
| -rw-r--r-- | monitor.c | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -1949,7 +1949,7 @@ static void tlb_info(Monitor *mon) #endif -#if defined(TARGET_SPARC) || defined(TARGET_PPC) +#if defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_XTENSA) static void tlb_info(Monitor *mon) { CPUState *env1 = mon_get_cpu(); @@ -2396,7 +2396,7 @@ static mon_cmd_t info_cmds[] = { .mhandler.info = hmp_info_pci, }, #if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) || \ - defined(TARGET_PPC) + defined(TARGET_PPC) || defined(TARGET_XTENSA) { .name = "tlb", .args_type = "", |