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authorRichard Henderson <richard.henderson@linaro.org>2020-08-19 21:50:35 -0700
committerRichard Henderson <richard.henderson@linaro.org>2020-09-01 07:41:38 -0700
commit78e9caf2f9410c8b90bb6d5a6449c750056c3f8a (patch)
tree06134b6ab56d5a35719527888600b8cb0420dd6a /linux-user
parentb2e80a3c191e90dee7ad05df303c237d9819bee4 (diff)
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target/microblaze: Split out ESR from env->sregs
Continue eliminating the sregs array in favor of individual members. Does not correct the width of ESR, yet. Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'linux-user')
-rw-r--r--linux-user/microblaze/cpu_loop.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c
index 3c69308..c10e3e0 100644
--- a/linux-user/microblaze/cpu_loop.c
+++ b/linux-user/microblaze/cpu_loop.c
@@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env)
case EXCP_HW_EXCP:
env->regs[17] = env->pc + 4;
if (env->iflags & D_FLAG) {
- env->sregs[SR_ESR] |= 1 << 12;
+ env->esr |= 1 << 12;
env->pc -= 4;
/* FIXME: if branch was immed, replay the imm as well. */
}
env->iflags &= ~(IMM_FLAG | D_FLAG);
- switch (env->sregs[SR_ESR] & 31) {
+ switch (env->esr & 31) {
case ESR_EC_DIVZERO:
info.si_signo = TARGET_SIGFPE;
info.si_errno = 0;
@@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env)
break;
default:
fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n",
- env->sregs[SR_ESR] & ESR_EC_MASK);
+ env->esr & ESR_EC_MASK);
cpu_dump_state(cs, stderr, 0);
exit(EXIT_FAILURE);
break;