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authorRichard Henderson <richard.henderson@linaro.org>2021-10-19 20:16:57 -0700
committerAlistair Francis <alistair@alistair23.me>2021-10-22 07:47:51 +1000
commite91a7227cb802ea62ffa14707ebc2f588b01213d (patch)
tree83e6aa01014f64717ecdcf2b0b7ee2b42ef44b72 /linux-user
parent99bc874fb3a0709c36ae4e594a1262ce1660e698 (diff)
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target/riscv: Split misa.mxl and misa.ext
The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'linux-user')
-rw-r--r--linux-user/elfload.c2
-rw-r--r--linux-user/riscv/cpu_loop.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index eb32f3e..f9b8261 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1448,7 +1448,7 @@ static uint32_t get_elf_hwcap(void)
uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
| MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
- return cpu->env.misa & mask;
+ return cpu->env.misa_ext & mask;
#undef MISA_BIT
}
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index 9859a36..e5bb6d9 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -133,7 +133,7 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
env->gpr[xSP] = regs->sp;
env->elf_flags = info->elf_flags;
- if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+ if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
exit(EXIT_FAILURE);
}