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| author | Suraj Jitindar Singh <sjitindarsingh@gmail.com> | 2019-11-28 14:46:54 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-12-17 10:39:48 +1100 |
| commit | 5d62725b2fefd59abf7225d620f7092fd34b8e11 (patch) | |
| tree | ea19cd6b909fdbadccafe83f993120d096668aed /linux-user | |
| parent | 2661f6ab2ba1694d7c19efdd622378817cb874ea (diff) | |
| download | qemu-5d62725b2fefd59abf7225d620f7092fd34b8e11.zip qemu-5d62725b2fefd59abf7225d620f7092fd34b8e11.tar.gz qemu-5d62725b2fefd59abf7225d620f7092fd34b8e11.tar.bz2 | |
target/ppc: Implement the VTB for HV access
The virtual timebase register (VTB) is a 64-bit register which
increments at the same rate as the timebase register, present on POWER8
and later processors.
The register is able to be read/written by the hypervisor and read by
the supervisor. All other accesses are illegal.
Currently the VTB is just an alias for the timebase (TB) register.
Implement the VTB so that is can be read/written independent of the TB.
Make use of the existing method for accessing timebase facilities where
by the compensation is stored and used to compute the value on reads/is
updated on writes.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[ clg: rebased on current ppc tree ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20191128134700.16091-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'linux-user')
| -rw-r--r-- | linux-user/ppc/cpu_loop.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/linux-user/ppc/cpu_loop.c b/linux-user/ppc/cpu_loop.c index d5704de..5b27f86 100644 --- a/linux-user/ppc/cpu_loop.c +++ b/linux-user/ppc/cpu_loop.c @@ -47,6 +47,11 @@ uint32_t cpu_ppc_load_atbu(CPUPPCState *env) return cpu_ppc_get_tb(env) >> 32; } +uint64_t cpu_ppc_load_vtb(CPUPPCState *env) +{ + return cpu_ppc_get_tb(env); +} + uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env) __attribute__ (( alias ("cpu_ppc_load_tbu") )); |