diff options
author | Michael Clark <mjc@sifive.com> | 2019-01-14 23:58:23 +0000 |
---|---|---|
committer | Palmer Dabbelt <palmer@sifive.com> | 2019-02-11 15:56:21 -0800 |
commit | fb73883964099011d34c052658e5ad8be049da61 (patch) | |
tree | 86f282b08a834767090233fdd02cc245b70e4561 /linux-user | |
parent | 7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3 (diff) | |
download | qemu-fb73883964099011d34c052658e5ad8be049da61.zip qemu-fb73883964099011d34c052658e5ad8be049da61.tar.gz qemu-fb73883964099011d34c052658e5ad8be049da61.tar.bz2 |
RISC-V: Use riscv prefix consistently on cpu helpers
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'linux-user')
-rw-r--r-- | linux-user/riscv/signal.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index f598d41..83ecc6f 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env) __put_user(env->fpr[i], &sc->fpr[i]); } - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/ + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR); __put_user(fcsr, &sc->fcsr); } @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc) uint32_t fcsr; __get_user(fcsr, &sc->fcsr); - csr_write_helper(env, fcsr, CSR_FCSR); + riscv_csr_write(env, CSR_FCSR, fcsr); } static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc) |