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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-01-07 13:32:32 -0800 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2022-01-11 18:40:44 +0100 |
| commit | 0b25c4a1f6345994d103ad08b2f4e1b366131dd9 (patch) | |
| tree | b71fb6e332d7b05ab594d650d3f426b18bb83d63 /linux-user/microblaze | |
| parent | 23ae825ab7af5e0a30c2d051e388e4e6aa618878 (diff) | |
| download | qemu-0b25c4a1f6345994d103ad08b2f4e1b366131dd9.zip qemu-0b25c4a1f6345994d103ad08b2f4e1b366131dd9.tar.gz qemu-0b25c4a1f6345994d103ad08b2f4e1b366131dd9.tar.bz2 | |
linux-user/microblaze: Fix SIGFPE si_codes
Fix a typo for ESR_EC_DIVZERO, which is integral not floating-point.
Fix the if ladder for decoding floating-point exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220107213243.212806-14-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'linux-user/microblaze')
| -rw-r--r-- | linux-user/microblaze/cpu_loop.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/linux-user/microblaze/cpu_loop.c b/linux-user/microblaze/cpu_loop.c index 08620d4..1a2556b 100644 --- a/linux-user/microblaze/cpu_loop.c +++ b/linux-user/microblaze/cpu_loop.c @@ -77,15 +77,25 @@ void cpu_loop(CPUMBState *env) env->iflags &= ~(IMM_FLAG | D_FLAG); switch (env->esr & 31) { case ESR_EC_DIVZERO: - si_code = TARGET_FPE_FLTDIV; + si_code = TARGET_FPE_INTDIV; break; case ESR_EC_FPU: - si_code = 0; - if (env->fsr & FSR_IO) { + /* + * Note that the kernel passes along fsr as si_code + * if there's no recognized bit set. Possibly this + * implies that si_code is 0, but follow the structure. + */ + si_code = env->fsr; + if (si_code & FSR_IO) { si_code = TARGET_FPE_FLTINV; - } - if (env->fsr & FSR_DZ) { + } else if (si_code & FSR_OF) { + si_code = TARGET_FPE_FLTOVF; + } else if (si_code & FSR_UF) { + si_code = TARGET_FPE_FLTUND; + } else if (si_code & FSR_DZ) { si_code = TARGET_FPE_FLTDIV; + } else if (si_code & FSR_DO) { + si_code = TARGET_FPE_FLTRES; } break; default: |