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author | Aleksandar Markovic <aleksandar.markovic@imgtec.com> | 2016-06-10 11:57:36 +0200 |
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committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-06-24 13:43:52 +0100 |
commit | 599bc5e89c46f95f86ccad0d747d041c89a28806 (patch) | |
tree | ac0fde39e6c036c145a5beba89e3a8b9975e0e50 /linux-user/main.c | |
parent | 87552089b62fa229d2ff86906e4e779177fb5835 (diff) | |
download | qemu-599bc5e89c46f95f86ccad0d747d041c89a28806.zip qemu-599bc5e89c46f95f86ccad0d747d041c89a28806.tar.gz qemu-599bc5e89c46f95f86ccad0d747d041c89a28806.tar.bz2 |
target-mips: Implement FCR31's R/W bitmask and related functionalities
This patch implements read and write access rules for Mips floating
point control and status register (FCR31). The change can be divided
into following parts:
- Add fields that will keep FCR31's R/W bitmask in procesor
definitions and processor float_status structure.
- Add appropriate value for FCR31's R/W bitmask for each supported
processor.
- Add function for setting snan_bit_is_one, and integrate it in
appropriate places.
- Modify handling of CTC1 (case 31) instruction to use FCR31's R/W
bitmask.
- Modify handling user mode executables for Mips, in relation to the
bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
reading and writing to FCR31.
- Modify gdb behavior in relation to FCR31.
Signed-off-by: Thomas Schwinge <thomas@codesourcery.com>
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'linux-user/main.c')
-rw-r--r-- | linux-user/main.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index fd88e22..78d8d04 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -4687,6 +4687,20 @@ int main(int argc, char **argv, char **envp) if (regs->cp0_epc & 1) { env->hflags |= MIPS_HFLAG_M16; } + if (((info->elf_flags & EF_MIPS_NAN2008) != 0) != + ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) { + if ((env->active_fpu.fcr31_rw_bitmask & + (1 << FCR31_NAN2008)) == 0) { + fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n"); + exit(1); + } + if ((info->elf_flags & EF_MIPS_NAN2008) != 0) { + env->active_fpu.fcr31 |= (1 << FCR31_NAN2008); + } else { + env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008); + } + restore_snan_bit_mode(env); + } } #elif defined(TARGET_OPENRISC) { |