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author | Richard Henderson <richard.henderson@linaro.org> | 2022-07-03 06:29:02 +0530 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2022-07-03 06:29:02 +0530 |
commit | e8e86b484eac70cd86e15fa10a2f0038a536cbba (patch) | |
tree | a7aa6d0ed2a00bd2ee768557b3f644265f73e13d /linux-user/loongarch64/target_resource.h | |
parent | ba45b82518bd5d9cad509765411e7f82a73aed53 (diff) | |
parent | 435774992e82d2d16f025afbb20b4f7be9b242b0 (diff) | |
download | qemu-e8e86b484eac70cd86e15fa10a2f0038a536cbba.zip qemu-e8e86b484eac70cd86e15fa10a2f0038a536cbba.tar.gz qemu-e8e86b484eac70cd86e15fa10a2f0038a536cbba.tar.bz2 |
Merge tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu into staging
Fifth RISC-V PR for QEMU 7.1
* Fix register zero guarding for auipc and lui
* Ensure bins (mtval) is set correctly
* Minimize the calls to decode_save_opc
* Guard against PMP ranges with a negative size
* Implement mcountinhibit CSR
* Add support for hpmcounters/hpmevents
* Improve PMU implenentation
* Support mcycle/minstret write operation
* Fixup MSECCFG minimum priv check
* Ibex (OpenTitan) fixup priv version
* Fix bug resulting in always using latest priv spec
* Reduce FDT address alignment constraints
* Set minumum priv spec version for mcountinhibit
* AIA update to v0.3 of the spec
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# gpg: Signature made Sun 03 Jul 2022 05:41:43 AM +0530
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20220703-1' of github.com:alistair23/qemu:
target/riscv: Update default priority table for local interrupts
target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
target/riscv: Set minumum priv spec version for mcountinhibit
hw/riscv: boot: Reduce FDT address alignment constraints
target/riscv: Don't force update priv spec version to latest
target/riscv: Ibex: Support priv version 1.11
target/riscv: Fixup MSECCFG minimum priv check
target/riscv: Support mcycle/minstret write operation
target/riscv: Add support for hpmcounters/hpmevents
target/riscv: Implement mcountinhibit CSR
target/riscv: pmu: Make number of counters configurable
target/riscv: pmu: Rename the counters extension to pmu
target/riscv: Implement PMU CSR predicate function for S-mode
target/riscv: Fix PMU CSR predicate function
target/riscv/pmp: guard against PMP ranges with a negative size
target/riscv: Minimize the calls to decode_save_opc
target/riscv: Remove generate_exception_mtval
target/riscv: Set env->bins in gen_exception_illegal
target/riscv: Remove condition guarding register zero for auipc and lui
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'linux-user/loongarch64/target_resource.h')
0 files changed, 0 insertions, 0 deletions