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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 22:40:23 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 86017ccfbd2b39371bd47dd7d2bed69ee184c3e5 (patch) | |
| tree | 8ad0692956642fab346c78636d4a771d77460809 /libdecnumber | |
| parent | 6efd55995a224787baa712500b82ef21a148d38e (diff) | |
| download | qemu-86017ccfbd2b39371bd47dd7d2bed69ee184c3e5.zip qemu-86017ccfbd2b39371bd47dd7d2bed69ee184c3e5.tar.gz qemu-86017ccfbd2b39371bd47dd7d2bed69ee184c3e5.tar.bz2 | |
target/microblaze: Fix width of FSR
The exception status register is only 32-bits wide. Do not use a
64-bit type to represent it. Since cpu_fsr is only used during
MSR and MTR instructions, we can just as easily use an explicit
load and store, so eliminate the variable.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'libdecnumber')
0 files changed, 0 insertions, 0 deletions