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| author | Blue Swirl <blauwirbel@gmail.com> | 2012-07-14 10:07:34 +0000 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-07-14 10:07:34 +0000 |
| commit | 6e2fe79da8853352e1cd401f86974c26b91ba3c8 (patch) | |
| tree | 2223f1c694ab9e81ceb26ae132f3c7df2ba4d9b4 /json-lexer.c | |
| parent | c0958559b1a589a0d189c45ea1adaa6b345f4256 (diff) | |
| parent | 3dde962f39717737b1031de129754f21eb77979f (diff) | |
| download | qemu-6e2fe79da8853352e1cd401f86974c26b91ba3c8.zip qemu-6e2fe79da8853352e1cd401f86974c26b91ba3c8.tar.gz qemu-6e2fe79da8853352e1cd401f86974c26b91ba3c8.tar.bz2 | |
Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
target-arm: Add support for long format translation table walks
target-arm: Implement TTBCR changes for LPAE
target-arm: Implement long-descriptor PAR format
target-arm: Use target_phys_addr_t in get_phys_addr()
target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
target-arm: Extend feature flags to 64 bits
target-arm: Implement privileged-execute-never (PXN)
ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits
hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits
target-arm: Fix TCG temp handling in 64 bit cp writes
target-arm: Fix some copy-and-paste errors in cp register names
target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
target-arm: Fix CP15 based WFI
Diffstat (limited to 'json-lexer.c')
0 files changed, 0 insertions, 0 deletions