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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2022-04-04 08:49:06 +0200 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-04-04 08:49:06 +0200 |
| commit | 7e5157696b97a5431ef8786e01bffe989c05493b (patch) | |
| tree | ccccaf2aaa5d475cb5994d98abeba60317a6c743 /include | |
| parent | ef95a244949a15b831876fe2d4e1320784729819 (diff) | |
| download | qemu-7e5157696b97a5431ef8786e01bffe989c05493b.zip qemu-7e5157696b97a5431ef8786e01bffe989c05493b.tar.gz qemu-7e5157696b97a5431ef8786e01bffe989c05493b.tar.bz2 | |
ppc/pnv: Fix number of registers in the PCIe controller on POWER9
The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.
Reported by Coverity (CID 1487176).
Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/pci-host/pnv_phb4.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index b02ecdc..19dcbd6 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -180,7 +180,7 @@ struct PnvPhb4PecState { MemoryRegion nest_regs_mr; /* PCI registers, excluding per-stack */ -#define PHB4_PEC_PCI_REGS_COUNT 0x2 +#define PHB4_PEC_PCI_REGS_COUNT 0x3 uint64_t pci_regs[PHB4_PEC_PCI_REGS_COUNT]; MemoryRegion pci_regs_mr; |