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| author | Bin Meng <bin.meng@windriver.com> | 2021-01-26 14:00:04 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-04 09:43:29 -0500 |
| commit | 8e3c886870d4cc5c3b93f2817edcc3699af31adc (patch) | |
| tree | a17e4dd7ed285d2fd9df9d4499e8e7e09513ef50 /include | |
| parent | 722f1352b6c248ead94efd77ff5726aa0cba949b (diff) | |
| download | qemu-8e3c886870d4cc5c3b93f2817edcc3699af31adc.zip qemu-8e3c886870d4cc5c3b93f2817edcc3699af31adc.tar.gz qemu-8e3c886870d4cc5c3b93f2817edcc3699af31adc.tar.bz2 | |
hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index de1464a..2656b39 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -127,7 +127,7 @@ enum { SIFIVE_U_PDMA_IRQ6 = 29, SIFIVE_U_PDMA_IRQ7 = 30, SIFIVE_U_QSPI0_IRQ = 51, - SIFIVE_U_GEM_IRQ = 0x35 + SIFIVE_U_GEM_IRQ = 53 }; enum { |