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authorPeter Maydell <peter.maydell@linaro.org>2017-01-20 11:15:09 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-01-20 11:15:09 +0000
commit6a228959081c12cc8a4f268ed00f77dbd0755404 (patch)
tree373b90ef2ae4b359aba35e97a1b6cde1cd475bc6 /include
parentb53db42bc0140a32e5196125b216a82d08992a7d (diff)
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hw/intc/arm_gic: Add external IRQ lines for VIRQ and VFIQ
Augment the GIC's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. We never use these, but it's helpful to keep the v2-and-earlier GIC's external interface in line with that of the GICv3 to avoid board code having to add extra code conditional on which version of the GIC is in use. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include')
-rw-r--r--include/hw/intc/arm_gic_common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index f4c349a..af3ca18 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -55,6 +55,8 @@ typedef struct GICState {
qemu_irq parent_irq[GIC_NCPU];
qemu_irq parent_fiq[GIC_NCPU];
+ qemu_irq parent_virq[GIC_NCPU];
+ qemu_irq parent_vfiq[GIC_NCPU];
/* GICD_CTLR; for a GIC with the security extensions the NS banked version
* of this register is just an alias of bit 1 of the S banked version.
*/