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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-04-08 15:15:31 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-22 14:44:52 +0100 |
| commit | ae3b3ba15c73320f75c121b08266a25a9e5d4edb (patch) | |
| tree | 1b247f393eee5c741a56072fae2f6c10196884e5 /include | |
| parent | c6dd2f9950cb59f7a02d57dcefef4d982efc6c7e (diff) | |
| download | qemu-ae3b3ba15c73320f75c121b08266a25a9e5d4edb.zip qemu-ae3b3ba15c73320f75c121b08266a25a9e5d4edb.tar.gz qemu-ae3b3ba15c73320f75c121b08266a25a9e5d4edb.tar.bz2 | |
hw/intc/arm_gicv3: Implement GICv4's new redistributor frame
The GICv4 extends the redistributor register map -- where GICv3
had two 64KB frames per CPU, GICv4 has four frames. Add support
for the extra frame by using a new gicv3_redist_size() function
in the places in the GIC implementation which currently use
a fixed constant size for the redistributor register block.
(Until we implement the extra registers they will RAZ/WI.)
Any board that wants to use a GICv4 will need to also adjust
to handle the different sized redistributor register block;
that will be done separately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-23-peter.maydell@linaro.org
Diffstat (limited to 'include')
| -rw-r--r-- | include/hw/intc/arm_gicv3_common.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 08b2778..40bc404 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -38,7 +38,12 @@ #define GICV3_LPI_INTID_START 8192 +/* + * The redistributor in GICv3 has two 64KB frames per CPU; in + * GICv4 it has four 64KB frames per CPU. + */ #define GICV3_REDIST_SIZE 0x20000 +#define GICV4_REDIST_SIZE 0x40000 /* Number of SGI target-list bits */ #define GICV3_TARGETLIST_BITS 16 |